1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as, for example, a gate array or ECA (Embedded Cell Array). In particular, the invention is concerned with a layout of a macrocell serving as a logic circuit such as AND circuit or flip-flop circuit used in the semiconductor integrated circuit, as well as peripheral circuit.
2. Description of the Prior Art
Recently, for improving the performance of transistor processing techniques, self-aligning type silicides such is as TiSi.sub.2 and CoSi.sub.2, called salicides, obtained by alloying a silicon surface layer with refractory metals such as titanium (Ti) and cobalt (Co), have been becoming popular. Generally, the resistance of source-drain regions or a well region of a field effect transistor which has been alloyed by the formation of a salicide layer is reduced to about one tenth of that of those produced without using the salicidation technique. A further technical improvement making the most of the features of salicide is now expected.
FIG. 20 is a configuration diagram showing a master chip image of a conventional embedded type gate array. In the drawing, the numerals 121 and 124 each denote a group of PMOS transistors, numerals 122 and 123 each denote a group of NMOS transistors, and numeral 125 denotes a peripheral circuit (I/O interface). Although gate arrays of channel fixed type, composite type and QTAT type are also known, an embedded type gate array will here be described from the standpoint of integration degree and device performance.
FIG. 21 shows a basic cell of a cell region of FIG. 20 for forming a logic circuit with a gate array or ECA. In the drawing, numeral 122 denotes a group of PMOS transistors, numeral 123 denotes a group of NMOS transistors, numerals 124, 125 and 126 denote gate, source-drain, and well regions, respectively, of the PMOS transistors, numerals 127, 128 and 129 denote gate, source-drain, and well regions, respectively, of the NMOS transistors, numerals 10a(1) to 10a(n) denote lateral wiring grids, and numerals 11a(1) to 11a(n) denote longitudinal wiring grids. Layout of a macrocell is made using an arrayed basic cell, and placement and wiring are performed for the macrocell to form a semiconductor integrated circuit having a logical function.
FIG. 4 is a layout diagram showing a three-input AND circuit formed by a conventional gate array or ECA, which is disclosed in JP-A-7/7141 . In the drawing, the numeral 1a denotes a power-supply line (VDD), numeral 1b denotes a ground line (GND), numeral 3 denotes a contact, numeral 1c denotes a first aluminum (Al) line, reference marks A, B and C denote input terminals of the three-input AND circuit, and Y denotes an output terminal thereof.
Usually, in a macrocell layout, as shown in FIG. 4, the gate, source-drain, and well regions are electrically connected using contacts 3 and the first aluminum wiring 1c, thereby affording a logical function. In this case, as many contacts are arranged as possible on the source-drain and well regions of transistors and are electrically connected using the first aluminum wiring to diminish the parasitic resistance of those regions. In some cases, for electrical connection of the macrocell, a second aluminum wiring and vias are used as connecting elements in the longitudinal direction.
By placement and wiring of such logic circuits as AND and flip-flop circuits, after layout in the above manner, there is obtained a semiconductor integrated circuit device. In this case, I/O connecting pins of macrocells are connected in such a manner that the first aluminum wiring is used for lateral wiring and the second aluminum wiring used for longitudinal wiring and the wiring are electrically connected together through vias or contacts.
FIG. 12 is a configuration diagram showing a conventional connection between transistors in a gate array or ECA and power-supply and ground wires, and FIG. 13 is a sectional view taken along line 13--13 in FIG. 12. In the drawings, numerals 84a and 84b denote first aluminum lines, numerals 83 denotes a contact, and numeral 81a and 81b denote a power-supply line and a ground line, respectively, which are usually metallic lines, say, aluminum lines. Generally, in a CMOS gate array, a PMOS transistor and an NMOS transistor are adjacent each other, and on one side of the PMOS transistor is disposed the power-supply line 81a which is constituted by the first aluminum wiring, while on one side of the NMOS transistor is disposed the ground line 81b. The power-supply line 81a is connected to a power supply of the chip at both chip ends, and the ground line 81b is connected to the ground of the chip, also at both chip ends.
For connecting the source region of the PMOS transistor to the power supply, the power-supply line 81a is connected to the source region of the PMOS transistor through the first aluminum line 84a, using plural contacts 83. On the other hand, for connecting the source region of the NMOS transistor to ground, the ground line 81b is connected to the source region of the NMOS transistor through the first aluminum line 84b, using contacts 83.
According to the conventional layout of a semiconductor integrated circuit such as gate array or ECA, for example in the case of the three-input AND circuit shown in FIG. 3 or 4 referred to above, the layout of the lateral wiring grid is wholly made using the first aluminum wiring. In the first Al wiring, therefore, the lateral wiring grid is not employable as a wiring region. Further, since the first Al wiring as the ground wiring is laid up and down of the macrocell, there has so far been a restriction such that a wiring layer such as the second Al wiring, other than the first Al wiring must be used as the longitudinal signal wiring. In the layout of a semiconductor integrated circuit device, both macrocell area and wiring area are required independently, so particularly in a complicated integrated circuit the wiring area becomes large, thus leading to an increase in the area of the semiconductor chip.
On the other hand, in the power-supply wiring and ground wiring, as shown in FIGS. 12 and 13, layout is made using the first Al wiring, but for connection thereof with the well region it is required to use many contacts 83 in order to diminish the resistance thereof. Further, it is likely that the aluminum which constitutes the first Al wiring may be influenced by electromigration and be broken during operation of the device.